ASIC Verification Engineer
The Company’s ASIC functional verification team is growing and requires talented, senior and above, verification engineers. Be responsible for the development of leading edge constrained-random verification methodologies and their successful application against innovative and disruptive data communication products.
Contribute in a very meaningful and visible way to the Company’s continuing success.
Define verification methodologies, and develop necessary verification infrastructure and tools.
Define, implement and deploy verification platforms, testbench architectures, and develop appropriate models and reusable VIP components
Develop detailed verification plans and schedules
Work closely with the design, software and system architecture teams to develop verification requirements.
Contribute to silicon bring-up and ASIC validation
- Required Skills/Experience
- 8+ years of directly related industry experience in ASIC/SOC verification
- 4+ years of demonstrable OVM or UVM experience
- Experience in the definition and development of verification infrastructure and simulation platform environments
- Experience of pseudo-random, coverage driven verification methodologies
- Expert knowledge of System Verilog and OVM or UVM
- Expert knowledge of simulation tools
- Desired Skills/Experience
- Knowledge of data center protocols such as Ethernet and TCP/IP
- Knowledge of SVA assertions
- FPGA verification experience
- SystemC, C or C++
- Perl, TCL and Pytho
- The successful candidate will have a BSEE or MSEE with a minimum of 8 Years of relevant experience in ASIC functional verification.
- Teamwork, good communication skills.
- Demonstrated problem solving skills coupled with attention to detail and enthusiasm for a right first time approach.
Email your resume to firstname.lastname@example.org and reference job posting RP1088R.
All candidates must be able to meet and work under Export Control requirements.